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cy7c1041dv33 4-mbit (256 k 16) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05473 rev. *k revised june 1, 2011 4-mbit (256 k 16) static ram features temperature ranges ? industrial: ?40 c to 85 c pin and function compatible with cy7c1041cv33 high speed ? t aa = 10 ns low active power ? i cc = 90 ma low cmos standby power ? i sb2 = 10 ma 2.0 v data retention automatic power-down when deselected ttl compatible inputs and outputs easy memory expansion with ce and oe features available in pb-free 48-ball vfbga, 44-pin (400-mil) molded soj, and 44-pin tsop ii packages functional description the cy7c1041dv33 is a high per formance cmos static ram organized as 256 k words by 16-bit s. to write to the device, take chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 to i/o 7 ) is written into the location specified on the address pins (a 0 to a 17 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 to i/o 15 ) is written into the location specified on the address pins (a 0 to a 17 ). to read from the device, take chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if ble is low, then data from the memory location specified by the address pins appears on i/o 0 to i/o 7 . if bhe is low, then data from memory appears on i/o 8 to i/o 15 . see the truth table on page 10 for a complete description of read and write modes. the input and output pins (i/o 0 to i/o 15 ) are placed in a high impedance state when the device is deselected (ce high), outputs are disabled (oe high), bhe and ble are disabled (bhe , ble high), or during a write operation (ce low and we low). the cy7c1041dv33 is available in a standard 44-pin 400-mil wide soj and 44-pin tsop ii package with center power and ground (revolutionary) pinout and a 48-ball fbga package. 14 15 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps input buffer 256k 16 a 0 a 11 a 13 a 12 a a a 16 a 17 a 9 a 10 io 0 ?io 7 oe io 8 ?io 15 ce we ble bhe logic block diagram [+] feedback
cy7c1041dv33 document number: 38-05473 rev. *k page 2 of 18 contents selection guide ................................................................ 3 pin configuration ............................................................. 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 dc electrical characteristics .......................................... 4 capacitance ...................................................................... 5 thermal resistance .......................................................... 5 ac test loads and waveforms ....................................... 5 ac switching characteristics ......................................... 6 data retention characteristics ....................................... 7 data retention waveform ................................................ 7 switching waveforms ...................................................... 7 truth table ...................................................................... 10 ordering information ...................................................... 11 ordering code definitions ..... .................................... 11 package diagrams .......................................................... 12 acronyms ........................................................................ 15 document conventions ................................................. 15 units of measure ....................................................... 15 document history page ................................................. 16 sales, solutions, and legal information ...................... 18 worldwide sales and design s upport ......... .............. 18 products .................................................................... 18 psoc solutions ......................................................... 18 [+] feedback
cy7c1041dv33 document number: 38-05473 rev. *k page 3 of 18 selection guide description -10 (industrial) unit maximum access time 10 ns maximum operating current 90 ma maximum cmos standby current 10 ma pin configuration figure 1. 48-ball vfbga (pinout 1) [1, 2] figure 2. 48-ball vfbga (pinout 2) [1, 2] figure 3. 44-pin soj/tsop ii we v cc a 11 a 10 nc a 6 a 0 a 3 ce io 2 io 0 io 1 a 4 a 5 io 3 io 5 io 4 io 6 io 7 v ss a 9 a 8 oe v ss a 7 io 8 bhe nc a 17 a 2 a 1 ble v cc io 9 io 10 io 11 io 12 io 13 io 14 io 15 a 15 a 14 a 13 a 12 nc nc nc 3 2 6 5 4 1 d e b a c f g h a 16 we v cc a 11 a 10 nc a 6 a 0 a 3 ce io 10 io 8 io 9 a 4 a 5 io 11 io 13 io 12 io 14 io 15 v ss a 9 a 8 oe v ss a 7 io 0 bhe nc a 17 a 2 a 1 ble v cc io 2 io 1 io 3 io 4 io 5 io 6 io 7 a 15 a 14 a 13 a 12 nc nc nc 3 2 6 5 4 1 d e b a c f g h a 16 1 2 3 4 5 6 7 8 9 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 a 17 18 17 20 19 27 28 25 26 22 21 23 24 a 16 a 15 a 0 a 1 a 2 a 3 a 4 a 7 a 6 a 14 a 13 a 12 a 11 a 9 a 8 a 10 oe bhe ble ce we io 0 io 1 io 2 io 3 io 4 io 5 io 6 io 7 io 8 io 9 io 10 io 11 io 12 io 13 io 14 io 15 v cc v cc v ss v ss nc 10 a 5 notes 1. nc pins are not connected on the die. 2. pinout 1 is compliant with cy7c1041cv33 and pinout 2 is jedec compliant. the difference between the two is that the higher an d lower byte i/os (i/o [7:0] and i/o [15:8] balls) are swapped. [+] feedback
cy7c1041dv33 document number: 38-05473 rev. *k page 4 of 18 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ..... ............ ............... ?65 ? c to +150 ? c ambient temperature with power applied .... .............. .............. .......... ?55 ? c to +125 ? c supply voltage on v cc relative to gnd [3] ...?0.3 v to +4.6 v dc voltage applied to outputs in high z state [3] .................................. ?0.3 v to v cc +0.3 v dc input voltage [3] .............................. ?0.3 v to v cc + 0.3 v current into outputs (low) ........................................ 20 ma static discharge voltage .......................................... > 2001 v (mil-std-883, method 3015) latch-up current .................................................... > 200 ma operating range range ambient temperature v cc speed industrial ?40 ? c to +85 ? c 3.3 v ? 0.3 v 10 ns dc electrical characteristics over the operating range parameter description test conditions -10 (industrial) unit min max v oh output high voltage v cc = min, i oh = ?4.0 ma 2.4 ? v v ol output low voltage v cc = min, i ol = 8.0 ma ? 0.4 v v ih [3] input high voltage 2.0 v cc + 0.3 v v il [3] input low voltage ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 ? a i oz output leakage current gnd < v out < v cc , output disabled ?1 +1 ? a i cc v cc operating supply current v cc = max, f = f max = 1/t rc 100 mhz ? 90 ma 83 mhz ? 80 ma 66 mhz ? 70 ma 40 mhz ? 60 ma i sb1 automatic ce power-down current ?ttl inputs max v cc , ce > v ih , v in > v ih or v in < v il , f = f max ?20ma i sb2 automatic ce power-down current ?cmos inputs max v cc , ce > v cc ? 0.3 v, v in > v cc ? 0.3 v, or v in < 0.3 v, f = 0 ?10ma note 3. minimum voltage is ?2.0 v and v ih (max) = v cc + 2 v for pulse durations of less than 20 ns. [+] feedback
cy7c1041dv33 document number: 38-05473 rev. *k page 5 of 18 capacitance parameter [4] description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 3.3 v 8 pf c out i/o capacitance 8pf thermal resistance parameter [4] description test conditions 48-ball fbga package 44-pin soj package 44-pin tsop ii package unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, four layer printed circuit board 27.89 57.91 50.66 ? c/w ? jc thermal resistance (junction to case) 14.74 36.73 17.17 ? c/w ac test loads and waveforms the ac test loads and waveform diagram follows. [5] 90% 10% 3.0 v gnd 90% 10% all input pulses * capacitive load consists of all components of the test environment rise time: 1 v/ns fall time: 1 v/ns 30 pf* output z = 50 ? 50 ? 1.5 v (b) (a) 3.3 v output 5 pf (c) r 317 ? r2 351 ? high z characteristics 10 ns device notes 4. tested initially and after any design or proce ss changes that may affect these parameters. 5. ac characteristics (except high z) are tested using the load conditions shown in ac test loads and waveforms (a). high z characteristics are tested for all speeds using the test load shown in ac test loads and waveforms (c). [+] feedback
cy7c1041dv33 document number: 38-05473 rev. *k page 6 of 18 ac switching characteristics over the operating range [6] parameter description ?10 (industrial) unit min max read cycle t power [7] v cc (typical) to the first access 100 ? ? s t rc read cycle time 10 ? ns t aa address to data valid ? 10 ns t oha data hold from address change 3 ? ns t ace ce low to data valid ? 10 ns t doe oe low to data valid ? 5 ns t lzoe oe low to low z [8] 0?ns t hzoe oe high to high z [8, 9] ?5ns t lzce ce low to low z [8] 3?ns t hzce ce high to high z [8, 9] ?5ns t pu ce low to power-up 0 ? ns t pd ce high to power-down ? 10 ns t dbe byte enable to data valid ? 5 ns t lzbe byte enable to low z 0 ? ns t hzbe byte disable to high z ? 6 ns write cycle [10, 11] t wc write cycle time 10 ? ns t sce ce low to write end 7 ? ns t aw address setup to write end 7 ? ns t ha address hold from write end 0 ? ns t sa address setup to write start 0 ? ns t pwe we pulse width 7?ns t sd data setup to write end 5 ? ns t hd data hold from write end 0 ? ns t lzwe we high to low z [8] 3?ns t hzwe we low to high z [8, 9] ?5ns t bw byte enable to end of write 7 ? ns notes 6. test conditions assume signal transition time of 3 ns or less , timing reference levels of 1.5 v, input pulse levels of 0 to 3 .0 v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 7. t power gives the minimum amount of time that the power supply should be at typical v cc values until the first memory access is performed. 8. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , t hzbe is less than t lzbe , and t hzwe is less than t lzwe for any given device. 9. t hzoe , t hzce , t hzbe, and t hzwe are specified with a load capacitance of 5 pf as in part (c) of ac test loads and waveforms . transition is measured when the outputs enter a high impedance state. 10. the internal write time of the memory is defined by the overlap of ce low and we low. ce and we must be low to initiate a write and the transition of either of these signals can terminate the write. the input data setup and hol d timing should be referenced to the leading edge of the sig nal that terminates the write. 11. the minimum write cycle time for write cycle no. 4 (we controlled, oe low) is the sum of t hzwe and t sd . [+] feedback
cy7c1041dv33 document number: 38-05473 rev. *k page 7 of 18 data retention characteristics over the operating range parameter description conditions [12] min max unit v dr v cc for data retention 2.0 ? v i ccdr data retention current v cc = v dr = 2.0 v, ce > v cc ? 0.3 v, v in > v cc ? 0.3 v or v in < 0.3 v ?10 ma t cdr [13] chip deselect to data retention time 0 ? ns t r [14] operation recovery time t rc ?ns data retention waveform switching waveforms figure 4. read cycle no. 1 [15, 16] 3.0 v 3.0 v t cdr v dr > 2 v data retention mode t r ce v cc previous data valid data valid t rc t aa t oha address data out notes 12. no input may exceed v cc + 0.3 v. 13. tested initially and after any design or proce ss changes that may affect these parameters. 14. full device operation requires linear v cc ramp from v dr to v cc(min.) > 50 ? s or stable at v cc(min.) > 50 ? s. 15. device is contin uously selected. oe , ce , bhe , and ble = v il . 16. we is high for read cycle. [+] feedback
cy7c1041dv33 document number: 38-05473 rev. *k page 8 of 18 figure 5. read cycle no. 2 (oe controlled) [17, 18] figure 6. write cycle no. 1 (ce controlled) [19, 20] switching waveforms (continued) 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzbe t pd high oe ce icc isb impedance address data out v cc supply t dbe t lzbe t hzce bhe , ble current i cc i sb t hd t sd t sce t sa t ha t aw t pwe t wc bw datai/o address ce we bhe, ble t notes 17. we is high for read cycle. 18. address valid prior to or coincident with ce transition low. 19. data i/o is high impedance if oe or bhe and ble = v ih . 20. if ce goes high simultaneously with we going high, the output remains in a high impedance state. [+] feedback
cy7c1041dv33 document number: 38-05473 rev. *k page 9 of 18 figure 7. write cycle no. 2 (ble or bhe controlled) figure 8. write cycle no. 3 (we controlled, oe high during write) [21, 22] switching waveforms (continued) t hd t sd t bw t sa t ha t aw t pwe t wc t sce datai/o address bhe ,ble we ce t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe data in valid ce address we data i/o oe note 23 bhe ,ble notes 21. data i/o is high impedance if oe or bhe and ble = v ih . 22. if ce goes high simultaneously with we going high, the output remains in a high impedance state. 23. during this period the i/os are in the out put state and input signals should not be applied. [+] feedback
cy7c1041dv33 document number: 38-05473 rev. *k page 10 of 18 figure 9. write cycle no. 4 (we controlled, oe low) truth table ce oe we ble bhe i/o 0 ?i/o 7 i/o 8 ?i/o 15 mode power h x x x x high z high z power-down standby (i sb ) l l h l l data out data out read all bits active (i cc ) l l h l h data out high z read lower bits only active (i cc ) l l h h l high z data out read upper bits only active (i cc ) l x l l l data in data in write all bits active (i cc ) l x l l h data in high z write lower bits only active (i cc ) l x l h l high z data in write upper bits only active (i cc ) l h h x x high z high z selected, outputs disabled active (i cc ) l x x h h high z high z selected, outputs disabled active (i cc ) switching waveforms (continued) t hd t sd t sce t ha t aw t pwe t wc t bw data i/o address ce we bhe , ble t sa t lzwe t hzwe note 24 note 24. during this period the i/os are in the out put state and input signals should not be applied. [+] feedback
cy7c1041dv33 document number: 38-05473 rev. *k page 11 of 18 ordering information speed (ns) ordering code package diagram package type operating range 10 cy7c1041dv33-10bvi 51-85150 48-ball vfbga pinout - 1 [25] industrial cy7c1041dv33-10bvxi 48-ball vfbga (pb-free) pinout - 1 [25] cy7c1041dv33-10bvjxi 48-ball vfbga (pb-free) pinout - 2 [25] cy7c1041dv33-10vxi 51-85082 44-pin (400-mil) molded soj (pb-free) cy7c1041dv33-10zsxi 51-85087 44-pin tsop ii (pb-free) please contact your local cypress sales re presentative for availability of these parts ordering code definitions temperature range: i = industrial pb-free package type: xxx = bv or bvj or v or zs bv = 48-ball vfbga pinout - 1 bvj = 48-ball vfbga pinout - 2 v = 44-pin (400-mil) molded soj zs = 44-pin tsop ii speed: 10 ns v33 = voltage range (3 v to 3.6 v) d = c9, 90 nm technology 1 = data width 16-bits 04 = 4-mbit density 1 = fast asynchronous sram family technology code: c = cmos 7 = sram cy = cypress c cy 1 v33 - 10 xxx 7 04 1 d i x note 25. pinout 1 is compliant with cy7c1041cv33 and pinout 2 is jedec compliant. the difference between the two is that the higher a nd lower byte i/os (i/o [7:0] and i/o [15:8] balls) are swapped. [+] feedback
cy7c1041dv33 document number: 38-05473 rev. *k page 12 of 18 package diagrams figure 1. 48-ball vfbga (6 8 1 mm) bv48/bz48, 51-85150 a 51-85150 *f [+] feedback
cy7c1041dv33 document number: 38-05473 rev. *k page 13 of 18 figure 2. 44-pin molded soj (400-mil) v44.4, 51-85082 package diagrams (continued) 51-85082 *c [+] feedback
cy7c1041dv33 document number: 38-05473 rev. *k page 14 of 18 figure 3. 44-pin tsop z44-ii, 51-85087 package diagrams (continued) 51-85087 *c [+] feedback
cy7c1041dv33 document number: 38-05473 rev. *k page 15 of 18 acronyms document conventions units of measure acronym description ce chip enable cmos complementary metal oxide semiconductor fbga fine-pitch ball grid array i/o input/output oe output enable soj small outline j-lead sram static random access memory tsop thin small outline package ttl transistor-transistor logic vfbga very fine-pitch ball grid array we write enable symbol unit of measure c degree celcius mhz mega hertz a micro amperes s micro seconds ma milli amperes mm milli meter ns nano seconds % percent pf pico farad vvolts wwatts [+] feedback
cy7c1041dv33 document number: 38-05473 rev. *k page 16 of 18 document history page document title: cy7c1041dv33, 4-mbit (256 k 16) static ram document number: 38-05473 rev. ecn no. orig. of change submission date description of change ** 201560 swi see ecn advance data sheet for c9 ipp *a 233729 rkf see ecn 1.ac, dc parameters are modified as per eros(spec # 01-2165) 2.pb-free offering in the ?ordering information? *b 351117 pci see ecn changed from advance to preliminary removed 15 and 20 ns speed bin corrected dc voltage (min) value in maximum ratings section from - 0.5 to - 0.3v redefined i cc values for com?l and ind?l temperature ranges i cc (com?l): changed from 100, 80 and 67 ma to 90, 80 and 75 ma for 8, 10 and 12ns speed bins respectively i cc (ind?l): changed from 80 and 67 ma to 90 and 85 ma for 10 and 12ns speed bins respectively added static discharge voltage and latch-up current spec added v ih(max ) spec in note# 2 changed note# 4 on ac test loads changed reference voltage level for measurement of hi-z parameters from ? 500 mv to ? 200 mv added data retention characteristics/waveform and footnote # 11, 12 added write cycle (we controlled, oe high during write) timing diagram changed package diagram name from 44-pin tsop ii z44 to 44-pin tsop ii zs44 and from 44-pin (400-mil) molded soj v34 to 44-pin (400-mil) molded soj v44 changed part names from z to zs in the ordering information table added 8 ns product information added pin-free ordering information shaded ordering information table *c 446328 nxr see ecn converted from preliminary to final removed -8 speed bin removed commercial operating range product information included automotive operating range product information updated thermal resistance table updated footnote #8 on high-z parameter measurement updated the ordering information and replaced package name column with package diagram in the ordering information table *d 480177 vkn see ecn added -10bvi product ordering code in the ordering information table *e 2541850 vkn/pyrs 07/22/08 added -10bvjxi part *f 2752971 vkn 08/18/2009 added automotive-a information for 12 ns speed, changed i sb1 spec from 25 ma to 15 ma for 12 ns speed, changed t doe and t dbe specs from 6 ns to 7 ns updated ordering information table *g 3034079 pras 09/20/2010 added ordering code definitions . added acronyms and units of measure . minor edits *h 3082285 hrp 11/09/2010 corrected typo in note 20. *i 3149096 aju 01/24/2011 no technical updates. *j 3182129 hrp 03/02/2011 no technical updates [+] feedback
cy7c1041dv33 document number: 38-05473 rev. *k page 17 of 18 *k 3271586 pras 06/01/2011 updated features (dislodged automotive part information to 001-69789). updated functional description (removed ?for best practice recommendations, refer to the cypress application note an1064, sram system guidelines.?). updated selection guide (dislodged automotive part information to 001-69789). updated operating range (dislodged automotive part information to 001-69789). updated dc electrical characteristics (dislodged automotive part information to 001-69789). updated ac switching characteristics (dislodged automotive part information to 001-69789). updated data retention characteristics (dislodged automotive part information to 001-69789). updated truth table . updated ordering information (dislodged automotive part information to 001-69789). updated in new template. document history page (continued) document title: cy7c1041dv33, 4-mbit (256 k 16) static ram document number: 38-05473 rev. ecn no. orig. of change submission date description of change [+] feedback
document number: 38-05473 rev. *k revised june 1, 2011 page 18 of 18 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c1041dv33 ? cypress semiconductor corporation, 2004-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback
mouser electronics authorized distributor click to view pricing, inventory, delivery & lifecycle information: cypress semiconductor: ? cy7c1041dv33-10bvi? cy7c1041dv33-10bvit? cy7c1041dv33-10bvxi? CY7C1041DV33-10BVXIT? cy7c1041dv33-10vxi? cy7c1041dv33-10vxit? cy7c1041dv33-10zsxi? cy7c1041dv33-10zsxit? cy7c1041dv33-10bvjxi? cy7c1041dv33-10bvjxit

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